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Old 07-25-2007, 05:45 PM
Chris Briggs
Posts: n/a
Default Re: variable clock frequency generation issue

SB wrote:
> I am working with a verilog behavioral model of a variable frequency
> clock.
> The model has two parts. The first part, through a series of case
> statements selects the period
> of the output clock signal. The second part of the model the
> generates
> the clock signal using the newly defined clock period.
> Hence the second part looks similar to:
> always
> begin
> #(half_period) clk_sig <= ~clk_sig;
> end

Has nothing to do with it being a real value. Has to do with that
thread blocking on a # delay and you can't change it while it's
waiting. However, you can abort it using disable. After the begin-end
is disabled, the always will restart it and it will use the new
half_period. Note: disable is non-synthesizable, but then, so are #

First, label the clock generator block, as in:

always begin : clock_gen
#(half_period) clk_sig = ~clk_sig;

And then, whenever half_period is updated, disable the block, as in:

always @(half_period)
disable clock_gen;

Alternatively, you could just add 'disable clock_gen;' after the
line(s) that changes half_period.

Also, as the other poster mentioned, there's usually no reason to use
a nonblocking assign in a clock generator.


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