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Old 07-25-2007, 05:11 PM
Posts: n/a
Default Re: variable clock frequency generation issue

On Jul 25, 5:33 am, SB <[email protected]> wrote:
> Hi there,
> I am working with a verilog behavioral model of a variable frequency
> clock.
> The model has two parts. The first part, through a series of case
> statements selects the period
> of the output clock signal. The second part of the model the
> generates
> the clock signal using the newly defined clock period.
> Hence the second part looks similar to:
> always
> begin
> #(half_period) clk_sig <= ~clk_sig;
> end

I wouldn't use a non-blocking assignment for this. In fact
I suspect you didn't either or your clock wouldn't work at

> The "half_period" term is a "real" quantity and its
> value is decided by a set of case statements of inputs
> to the block. I am using a real as the half_period is often assigned
> very large decimal values with fractional components.
> I wish that once the half_period value is updated, that the
> clock signal generation code in the always block uses this new value
> immediately. However, I
> am finding that the clk_sig waveform does not use a new
> value of half_period until the previous value of half_period has
> completely
> elapsed in the timing waveform.
> Can anybody suggest what how I should correct this and
> ensure that the "always" block will instantaneously pick-up
> the new value of the "half_period"?
> I have tried using $realtobits on the half_period and using
> the resulting wire in a sensitivity list on the always statement
> but this does not work.

This sounds similar to what I would suggest. In what way
didn't it work? Did the compiler give an error or does it
just not do what you want? Did you write something like...

always @ (clk_sig or half_period_bits)
clk_sig = #(half_period) ~clk_sig;

> Thanks in advance
> SB

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