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Old 04-08-2007, 06:59 PM
Verictor
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Default Re: inferring a dual port memory

On Apr 8, 3:14 am, "rjain" <[email protected]> wrote:
> On Apr 5, 11:03 pm, "Verictor" <[email protected]> wrote:
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> > On Apr 5, 10:48 am, "Mike Lewis" <[email protected]> wrote:

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> > > "John_H" <[email protected]> wrote in message

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> > >news:[email protected]

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> > > > "Verictor" <[email protected]> wrote in message
> > > >news:[email protected] oups.com...
> > > > <snip>
> > > >> Right. I am working on an ASIC target. My tools are Physical Compiler
> > > >> and a 130nm process. I tried before I posted my question. It just
> > > >> didn't provide what I need. Can you tell me what to look at when it
> > > >> infers cells?

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> > > >> Thanks a lot

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> > > > I can't, perhaps someone else can.

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> > > > The Physical Compiler documentation may include specific documentation on
> > > > inferring memories. It's important enough in my FPGA work that the
> > > > synthesis tools I work with have several pages dedicated to memory
> > > > inference. It may be that you need to instantiate dual ports in this
> > > > tool. It may be that you need to have two versions of the address to get
> > > > the synthesis to recognize it as two ports rather than a malformed single
> > > > port memory; this was a problem for another poster recently. If you can't
> > > > find documentation, try the technical support you're already paying dearly
> > > > for.

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> > > In the ASIC world you have to instantiate the specific memory block that you
> > > want to use. The sysnthesizer won't infer a memory ... it will just create
> > > FFs.

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> > > Mike- Hide quoted text -

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> > > - Show quoted text -

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> > Thanks for the comment. Doesn't the DesignWare is coming in to do the
> > inferring job?

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> For asic design, for memories, generally memory compilers from third
> party vendors like artisan/virage etc are used to generate simulation
> model/synthesis model/layout hard macro, and instantiated directly
> instead of synthesis tool inferring it...
> If you allow synthesis tool, it will always implement it using regular
> flops with a big area/power penality. By using memories from other
> vendors, you have many options like latch based, high density flop
> based, true SRAM etc...
> I don't think designware compiles memories...- Hide quoted text -
>
> - Show quoted text -


This is new to me. Do you have relevant documentation how to
instantiate the models?

Thanks

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