View Single Post
  #6 (permalink)  
Old 04-05-2007, 07:03 PM
Verictor
Guest
 
Posts: n/a
Default Re: inferring a dual port memory

On Apr 5, 10:48 am, "Mike Lewis" <[email protected]> wrote:
> "John_H" <[email protected]> wrote in message
>
> news:[email protected]
>
>
>
>
>
> > "Verictor" <[email protected]> wrote in message
> >news:[email protected] oups.com...
> > <snip>
> >> Right. I am working on an ASIC target. My tools are Physical Compiler
> >> and a 130nm process. I tried before I posted my question. It just
> >> didn't provide what I need. Can you tell me what to look at when it
> >> infers cells?

>
> >> Thanks a lot

>
> > I can't, perhaps someone else can.

>
> > The Physical Compiler documentation may include specific documentation on
> > inferring memories. It's important enough in my FPGA work that the
> > synthesis tools I work with have several pages dedicated to memory
> > inference. It may be that you need to instantiate dual ports in this
> > tool. It may be that you need to have two versions of the address to get
> > the synthesis to recognize it as two ports rather than a malformed single
> > port memory; this was a problem for another poster recently. If you can't
> > find documentation, try the technical support you're already paying dearly
> > for.

>
> In the ASIC world you have to instantiate the specific memory block that you
> want to use. The sysnthesizer won't infer a memory ... it will just create
> FFs.
>
> Mike- Hide quoted text -
>
> - Show quoted text -


Thanks for the comment. Doesn't the DesignWare is coming in to do the
inferring job?

Reply With Quote