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Old 04-05-2007, 04:16 PM
Verictor
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Default Re: inferring a dual port memory

On Apr 4, 3:25 pm, "John_H" <[email protected]> wrote:
> "Verictor" <[email protected]> wrote in message
>
> news:[email protected] ups.com...
>
>
>
> > Hi,

>
> > I try to infer a dual port RAM after synthesis. DesignWare maybe a
> > good candidate doing this but I have never used it before. So if
> > someone who had applied it before can provide a very simple example
> > that would be very helpful.

>
> > My dual port RAM model is described in the following pseudo code
> > (detail skipped)

>
> > always @(posedge clock) begin : read
> > Temp_reg <= memory[address];
> > end

>
> > always @(negedge clock) begin: write
> > memory[address] <= Temp_reg;
> > end

>
> > Thanks

>
> As long as the address is a registered value, synthesizers such as
> SynplifyPro will infer the dual-port for an FPGA target.
>
> If you're working with an ASIC target, it is very specific to your tool set
> and target silicon as far as what infers, what doesn't, and how.



Right. I am working on an ASIC target. My tools are Physical Compiler
and a 130nm process. I tried before I posted my question. It just
didn't provide what I need. Can you tell me what to look at when it
infers cells?

Thanks a lot

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