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Old 04-04-2007, 09:31 PM
Verictor
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Default inferring a dual port memory

Hi,

I try to infer a dual port RAM after synthesis. DesignWare maybe a
good candidate doing this but I have never used it before. So if
someone who had applied it before can provide a very simple example
that would be very helpful.

My dual port RAM model is described in the following pseudo code
(detail skipped)

always @(posedge clock) begin : read
Temp_reg <= memory[address];
end

always @(negedge clock) begin: write
memory[address] <= Temp_reg;
end

Thanks

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