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 Uwe Bonnes Guest Posts: n/a Re: Inferring a pipelined multiplexer

glen herrmannsfeldt <[email protected]> wrote:
....
> (snip)

> If you want to pipeline it you will need a register in between.

Isn't counter_p[] the register in between?

> Otherwise it is up to the synthesis software to find the best logic,
> which may be a 64 to 1 multiplexer. If you put a register in between,
> that should fix it.

I still wonder where the difference between
for (j=0; j<8; j = j+1)
counter_p[j]<= counter[{sel[N_BITS-1:3], j[2:0]}];
and
for (j=0; j<8; j = j+1)
case (sel[N_BITS-1:3])
3'h0: counter_p[j]<= counter[{3'h0, j[2:0]}];
3'h1: counter_p[j]<= counter[{3'h1, j[2:0]}];
3'h2: counter_p[j]<= counter[{3'h2, j[2:0]}];
3'h3: counter_p[j]<= counter[{3'h3, j[2:0]}];
3'h4: counter_p[j]<= counter[{3'h4, j[2:0]}];
3'h5: counter_p[j]<= counter[{3'h5, j[2:0]}];
3'h6: counter_p[j]<= counter[{3'h6, j[2:0]}];
3'h7: counter_p[j]<= counter[{3'h7, j[2:0]}];
endcase // case (sel[N_BITS-1:3])

is....
--
Uwe Bonnes [email protected]

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