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Old 03-08-2007, 02:52 PM
Uwe Bonnes
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Default Re: Inferring a pipelined multiplexer

Uwe Bonnes <[email protected]> wrote:
> Hallo,


> for one design I have 64 8 bit counters, where I need to read out one
> counter pointed to by input 'sel' to output 'data'. Multiplexing should be
> down in a two stage process, first 8 pieces 8-bit 8-to-1 multiplexer and in
> the second stage a single 8-bit 8-to-1 multiplexer. The module boils down
> to:

....
to partially answer my own question:
The unconnected nodes were caused by the mismatch in width of the counters
and data .

Coding
for (j=0; j<8; j = j+1)
case (sel[N_BITS-1:3])
3'h0: counter_p[j]<= counter[{3'h0, j[2:0]}];
3'h1: counter_p[j]<= counter[{3'h1, j[2:0]}];
3'h2: counter_p[j]<= counter[{3'h2, j[2:0]}];
3'h3: counter_p[j]<= counter[{3'h3, j[2:0]}];
3'h4: counter_p[j]<= counter[{3'h4, j[2:0]}];
3'h5: counter_p[j]<= counter[{3'h5, j[2:0]}];
3'h6: counter_p[j]<= counter[{3'h6, j[2:0]}];
3'h7: counter_p[j]<= counter[{3'h7, j[2:0]}];
endcase // case (sel[N_BITS-1:3])

makes the HDL analysis infer the 8 8-to-1 multiplexes as expected. Is the
HDL analysis at fault or my coding style?

--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
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