Thread: issue
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Old 09-14-2006, 06:10 AM
rik
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Posts: n/a
Default Re: issue

Thanks Jerry for your reply.
I had some typos in my question. the code is like,

always @(ipconfig)
if ( ipconfig)
begin
if (shiftreg_dr[34:32] == `ADDR_BASE)
base_addr_reg = shiftreg_dr[31:0];
.........

always @(bus_done, fill)
if (fill & bus_done)
begin
base_addr_reg = base_addr_reg + 1;
bus_address = base_addr_reg;
.....................
....................

The bottomline is, my base_addr_reg will be initialized in the ipconfig
mode and it will be used and incremented in fill mode. People can say
why I am not using under the same always block.
One thing is for sure that fill and ipconfig doesnot coexist.



Jerry Johns wrote:
> what you can do is add all four signals (test_clk, ipconfig, fill,
> bus_done) to ur sensitivity list (always @ (....)), and then write a
> branched if from there
>
> i dont think the compiler will let u compile this code
>
> rik wrote:
> > hi guys
> >
> > I am new yo verilog. i have an issue on assigning a register in
> > different always block. If I dont do it its making my design more
> > complex.
> >
> > always @(Test_clk)
> > if (Test_clk & ipconfig)
> > begin
> > if (shiftreg_dr[34:32] == `ADDR_BASE)
> > base_addr_reg = shiftreg_dr[31:0];
> > ...........
> >
> > In the above always block I am assigning my initial address to the
> > base_addr_reg. According to my design, after many clock cycles I will
> > be in the fill mode.
> > In the fill mode if my transaction is complete, I increment my address
> > to invoke my next transaction.
> >
> > always @(bus_done, fill)
> > if (fill & bus_done)
> > begin
> > base_addr_reg = base_addr_reg + 1;
> > bus_address = base_addr_reg;
> >
> > My question is can I increment the base_addr_reg in the second always
> > block instead of the first where is gets initialized? The "fill" &
> > "ipconfig" mode doesnot take place at the same time.So is it
> > synthesizable???
> >
> >
> > Thanks for your reply in advance.
> >
> > Rik


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