Thread: issue
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Old 09-13-2006, 08:24 PM
rik
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Default issue

hi guys

I am new yo verilog. i have an issue on assigning a register in
different always block. If I dont do it its making my design more
complex.

always @(Test_clk)
if (Test_clk & ipconfig)
begin
if (shiftreg_dr[34:32] == `ADDR_BASE)
base_addr_reg = shiftreg_dr[31:0];
............

In the above always block I am assigning my initial address to the
base_addr_reg. According to my design, after many clock cycles I will
be in the fill mode.
In the fill mode if my transaction is complete, I increment my address
to invoke my next transaction.

always @(bus_done, fill)
if (fill & bus_done)
begin
base_addr_reg = base_addr_reg + 1;
bus_address = base_addr_reg;

My question is can I increment the base_addr_reg in the second always
block instead of the first where is gets initialized? The "fill" &
"ipconfig" mode doesnot take place at the same time.So is it
synthesizable???


Thanks for your reply in advance.

Rik

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