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Old 08-15-2006, 07:38 PM
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Default Re: Inferring dual port two output sram

> >I wish to infer a dual port SRAM with one input write data port and two
> >output read data ports. Ideally I'd like describe this abstractly
> >enough so that the code will generate the correct hardware for my
> >prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
> >library (memory to be inferred via Synopsys Designware).

> I haven't used Designware recently but I'd be very surprised if they
> added memory inferring to its features. In ASICs one needs to run a
> memory compiler which is specific to each process and it's supplied by
> the library vendor (or another third party memory IP vendor). So you
> probably will have to run a memory compiler get a model and
> instantiate that model in your design. If so it makes more sense to do
> the same for the FPGA flow too.

aha :-( thanks for clearing that up.

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