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Old 08-15-2006, 03:48 PM
John_H
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Default Re: Inferring dual port two output sram

Sorry, it's early... I see now you don't need the read value during the
write. Define a wire for one of the addresses that looks like
rwaddr = wr_en? waddr : raddr0;
and use the rwaddr in both the write and appropriate read.


[email protected] wrote:
> Hi,
>
> I wish to infer a dual port SRAM with one input write data port and two
> output read data ports. Ideally I'd like describe this abstractly
> enough so that the code will generate the correct hardware for my
> prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
> library (memory to be inferred via Synopsys Designware). The following
> code in ISE results in 2 dual port memories with a single input and
> output - which is not what I want
>
> always @(posedge clk)
> begin
> if (wr_en)
> ram[waddr] <= data_in;
> end
> //-----------------------------------------------------------------------
>
> always @(posedge clk)
> begin
> if(rst_n ==1'b0)
> begin
> data_out0 <= 'b0;
> data_out1 <= 'b0;
> end
> else
> if(wr_en!=1'b1)
> begin
> data_out0 <= ram[raddr0];
> data_out1 <= ram[raddr1];
> end
> end
>
> Any suggestions would be most welcome!
> thanks
>

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