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Old 08-15-2006, 03:45 PM
Posts: n/a
Default Re: Inferring dual port two output sram

For a dual port memory in the Xilinx architecture, each port has one
address, not two addresses. You specify a waddr which is different than
raddr0 and raddr1. You're describing a three port memory. If you can
use a 2x clock for the memory, it's simple to enable the write on the
equivalent of the 1x clock rising edge and the read on the 1x clk
falling edge by delivering the 2x clk with the write enable in the
correct place. The address also needs to be muxed but muxes are fast.

[email protected] wrote:
> Hi,
> I wish to infer a dual port SRAM with one input write data port and two
> output read data ports. Ideally I'd like describe this abstractly
> enough so that the code will generate the correct hardware for my
> prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
> library (memory to be inferred via Synopsys Designware). The following
> code in ISE results in 2 dual port memories with a single input and
> output - which is not what I want
> always @(posedge clk)
> begin
> if (wr_en)
> ram[waddr] <= data_in;
> end
> //-----------------------------------------------------------------------
> always @(posedge clk)
> begin
> if(rst_n ==1'b0)
> begin
> data_out0 <= 'b0;
> data_out1 <= 'b0;
> end
> else
> if(wr_en!=1'b1)
> begin
> data_out0 <= ram[raddr0];
> data_out1 <= ram[raddr1];
> end
> end
> Any suggestions would be most welcome!
> thanks

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