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Old 08-15-2006, 03:41 PM
gabor
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Default Re: Inferring dual port two output sram


[email protected] wrote:
> Hi,
>
> I wish to infer a dual port SRAM with one input write data port and two
> output read data ports. Ideally I'd like describe this abstractly
> enough so that the code will generate the correct hardware for my
> prototype FPGA platform (xilinx Spartan 3) and also when using an ASIC
> library (memory to be inferred via Synopsys Designware). The following
> code in ISE results in 2 dual port memories with a single input and
> output - which is not what I want
>
> always @(posedge clk)
> begin
> if (wr_en)
> ram[waddr] <= data_in;
> end
> //-----------------------------------------------------------------------
>
> always @(posedge clk)
> begin
> if(rst_n ==1'b0)
> begin
> data_out0 <= 'b0;
> data_out1 <= 'b0;
> end
> else
> if(wr_en!=1'b1)
> begin
> data_out0 <= ram[raddr0];
> data_out1 <= ram[raddr1];
> end
> end
>
> Any suggestions would be most welcome!
> thanks


To end up with one dual-port memory, one of the outputs
in the second process needs to use the same address
as the write section, i.e. replace either raddr0 or raddr1
with waddr. Otherwise this can't be implemented in a
single DP RAM. What you've described is a quasi three
port memory (1 write and 2 read) since you have three
address buses.

Regards,
Gabor

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