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Old 06-19-2006, 01:39 AM
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Default Re: Estimate gate count in Verilog?

I would add that synthesis results will also vary as a result of your
timing and power budgets, coupled with temperature range, supply
requirements, technology and the particular library you use for
synthesis. For instance, the tighter your timing constraints are, the
more the synthesis engine will try to do in parallel, driving up your
Cadence Design Systems ( and Synopsys
( both make synthesis products (RTL Compiler and
Design Analyzer respectively). You might check out their websites for
whitepapers on the subject.
Mike S.

General Schvantzkoph wrote:
> On Tue, 13 Jun 2006 06:31:43 -0700, Davy wrote:
> > Hi,
> >
> > When I design a circuit, how to estimate gate count? Is there any
> > reference?
> >
> > And is it related to the technology like 180nm or 90nm?
> >
> > Thanks!
> > Davy

> You run it through a synthesis tool. Your gut should be able to give you
> an approximate size, assuming you have a lot of experience with a
> particular synthesis tool and technology, but the only way to get a count
> that means anything is to synthesize the design.

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