Re: Describing pipelined hardware
Jonathan,
I've successfully used register balancing in Synopsys DC since about
eight years ago. In order to notify the other end about when there's
work to be done, it is often a good idea to pass a synchronization
signal (e.g. data valid, deasserted reset) through the pipeline as
well.
Don't forget your post-synthesis verification though (gate-level or
formal). We never completely trust the tools, right?
Regards,
Marcus
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