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Old 05-27-2006, 05:29 AM
unfrostedpoptart
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Default Re: Declaring an output as 'not connected'


Joe wrote:
> When I instantiate a module and leave one of its output non connected,
> I get a warning complaining that the output was left open (I am using
> Xilinx ISE 8.1i).
>
> Is there a way (or a trick) to declare in Verilog that a certain output
> port is intentionally not connected? (and by that, avoiding the warning
> message).


This is tool-specific: there's no answer that will work with
everything. ISE, since 7.1, has had very extensive warning/error
filtering. Look at the docs to see how to use it.

David

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