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Old 05-27-2006, 12:24 AM
Joe
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Default Declaring an output as 'not connected'

When I instantiate a module and leave one of its output non connected,
I get a warning complaining that the output was left open (I am using
Xilinx ISE 8.1i).

Is there a way (or a trick) to declare in Verilog that a certain output
port is intentionally not connected? (and by that, avoiding the warning
message).

Thanks,

Joe

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