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Old 05-18-2006, 06:44 PM
Jeremy Ralph
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Default Re: how i declare array for input port


Certainly Ralf's wire technique is supported. Arrays are permitted for
wires or regs, but ARRAYS ARE NOT PERMITTED FOR INPUTS OR OUTPUTS IN
VERILOG as Steve already mentioned. Thus, arrays can only be used
*within* a module and you need to flatten the array into a single
dimensional vector for ports. Then wherever you instantiate the
module, you can map the input and outputs back into a array (reg or
wire) for ease of use in the instantiating (parent) module.

SystemVerilog supports array ports.



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kunal wrote:
> but the wire is not supported
> i used like
> module mux8_1 (in, sel, out);
> input [1:0] in [7:0];// input is array of 8 bit of 2 bit width
> input[2:0] sel;
> output[1:0] out;
> reg[1:0] out;
>
> always @(in or sel)
> begin
> case (sel)
> 3'b000 : out = in[0];
> 3'b001 : out = in[1];
> 3'b010 : out = in[2];
> 3'b011 : out = in[3];
> 3'b100 : out = in[4];
> 3'b101 : out = in[5];
> 3'b110 : out = in[6];
> default : out = in[7];
> endcase
> end
> endmodule
> how i declare aaray having width like above to work mux properly.


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