View Single Post
  #3 (permalink)  
Old 05-17-2006, 07:52 PM
Ralf Hildebrandt
Guest
 
Posts: n/a
Default Re: how i declare array for input port

Stephen Williams wrote:

>> if i declare array for input port like input [1:0] in [7:0];


> You can't have an array for a port, input or output, in Verilog.


-> Transform the 2D-vector into a 1D-vector: input inp [15:0];
You map map it to a 2D-vector inside the module - if you really need it.

Ralf
Reply With Quote