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Old 05-15-2006, 09:07 PM
Pinhas
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Default icarus/cver and OpenRISC/or1k (orp_soc) from open core

Hi
Does somebody has experience with this core and free verilog
sorp_socimulators. If so please recommend a fix.

cver compiles and runs it okay. The log files and dump are created. In
VCD dump some signals like of module sram_top are high Z and should be
1/0 (no three state).

icarus crashes during compilation. This is a very big design and I
tried to figure out what is wrong by removing files. I made some
progress but still icarus crashes.

.../../rtl/verilog/xsv_fpga_top.v:1067: warning: Port 7 (wb_adr_i) of
ps2_top expects 4 bits, got 32.
.../../rtl/verilog/xsv_fpga_top.v:1067: : Leaving 28 high bits of
the expression dangling.
.../../bench/verilog/xess_top.v:134544377: warning: Port 26 (vga_r) of
xsv_fpga_top expects 4 bits, got 2.
.../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
of the port unconnected.
.../../bench/verilog/xess_top.v:134544377: warning: Port 27 (vga_g) of
xsv_fpga_top expects 4 bits, got 2.
.../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
of the port unconnected.
.../../bench/verilog/xess_top.v:134544377: warning: Port 28 (vga_b) of
xsv_fpga_top expects 4 bits, got 2.
.../../bench/verilog/xess_top.v:134544377: : Leaving 2 high bits
of the port unconnected.
.../../bench/verilog/xess_top.v:134544377: warning: Port 40 (eth_txd) of
xsv_fpga_top expects 4 bits, got 5.
.../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
of the expression dangling.
.../../bench/verilog/xess_top.v:134544377: warning: Port 44 (eth_rxd) of
xsv_fpga_top expects 4 bits, got 5.
.../../bench/verilog/xess_top.v:134544377: : Leaving 1 high bits
of the expression dangling.
ivl: cprop.cc:938: virtual void cprop_functor::lpm_mux(Design*,
NetMux*): Assertion `obj->pin_Data(idx, 0).nexus()->drivers_constant()
&& obj->pin_Data(idx, 1).nexus()->drivers_constant()' failed.
sh: line 1: 19919 Done /usr/local/lib/ivl/ivlpp -L
-D__ICARUS__=1 -f/tmp/ivrlg6a558351 -I../../bench/verilog
-I../../bench/models/28f016s3 -I../../rtl/verilog
-I../../rtl/verilog/mem_if -I../../rtl/verilog/dbg_interface
-I../../rtl/verilog/ssvga -I../../rtl/verilog/ethernet
-I../../rtl/verilog/uart16550 -I../../rtl/verilog/ps2
-I../../rtl/verilog/or1200 -I../../lib/altera
19920 Aborted | /usr/local/lib/ivl/ivl
-C/tmp/ivrlh6a558351 -C/usr/local/lib/ivl/vvp.conf -- -

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