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Old 05-15-2006, 07:21 PM
Jeremy Ralph
Posts: n/a
Default Re: Read a reg value from the outer module without declaring port

Ooops... this is the comp.lang.verilog not comp.lang.vhdl as my
previous message assumed.

Verilog does allow you to access internals using 'hierarchical
referencing'. For example:

always @(topmodule.innermodule.regname)
$display("reg value is %0d", topmodule.innermodule.regname);

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