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Old 05-15-2006, 07:09 PM
Jeremy Ralph
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Default Re: Read a reg value from the outer module without declaring port

Unfortunately, to the best of my knowledge, VHDL doesn't allow you to
sniff signals that are buried within a hierarchy, like Verilog does.
Your simulator should allow you to probe and force such values though.

VHDL does however allow global signals which can be useful for
verification purposes. To create a global signal create a package with
a signal definition in it. Then you will have access to the signal
from wherever you include the package.

---
PDTi [ http://www.productive-eda.com ]
SpectaReg -- Spec-down code and doc generation for register maps

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