I haven't had time to load Xilinx's tools (sometime I'm going to have
to do it for another project) to see what there DPRAM library device
looks like.

The solution I was going to offer was going to be a time division
solution like rhnlogic suggested. Relative to the reading/writing of
the ports of the DPRAM, what clocks are available? What other controls
signals are present that could be taken advantage of?

If you want to reinvent the wheel you could implement your own dual
port memory. It would probably be a little bit more than 6240 flip
flops if you can limit the address to 130 range and if you're sloppy
about it 16384 flip flops for the whole 256 range. (plus addressing and
control support)

Derek