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Old 03-02-2006, 09:06 AM
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Default ASIC Architect positions at Nvidia

Current opening in Company: NVIDIA www.nvidia.com ,
http://www.nvidia.com/page/home.html



Nvidia, (Nasdaq: NVDA) are worldwide market leader in Programmable
Graphic Processor Technologies. NVIDIA is a market leader in graphics
and digital media processors. NVIDIA graphics processing units (GPUs),
media and communications processors (MCPs), and wireless media
processors (WMPs) have broad market reach and are incorporated into a
variety of platforms, including consumer and enterprise PCs, notebooks,
workstations, mobile phones, PDAs, and game consoles. NVIDIA's
customers are OEMs, add-in card manufacturers, system builders, and
consumer electronics companies worldwide who choose NVIDIA technology
as a core component for their solutions. NVIDIA's award-winning
products deliver superior performance and reliability for graphics,
video, and communications solutions in the areas of manufacturing,
science, multimedia, entertainment, and education.



Senior ASIC Design positions:

Responsibilities:- ASIC Design for Digital Media Processor and HDTV
Systems. Micro-architecture definition; working closely with graphics,
video and system architects. RTL design, verification, emulation,
synthesis, timing, and silicon bring-up. Understand high speed system
design and layout issues. High speed bus signal integrity
debug/characterization. Interfacing with the ASIC design organization
to understand limitations of products, build functional and timing
specifications for customers. Interfacing with the System design
organization to keep up to speed on latest technologies, processes and
working with customers to integrate discoveries into their processes.

Minimum requirements:

Senior or Lead ASIC / Logic Design engineers with previous experience
in Graphics, Video, Microprocessor Design, SOC design, or Multimedia
ASIC design. Strong logic design and verification skills.Verilog and
Synopsys experience required. Primetime experience desirable.
Programming skills in C and/or PERL. Good communication skills and
proven ability to work well within a team. The ideal candidate will be
familiar with all stages in the ASIC design flow including DFT, timing
analysis, floorplanning, ECO flow, silicon bringup, and ATE test
support. BS in Electrical Engineering, MS preferred. EOE

Another Position: GRAPHICS ARCHITECT

Roles include some or all of the below:

- Develop algorithms and design hardware extending the state
of the art in hardware support for computer graphics. Working within a
team, graphics architects document, design, develop functional and
performance simulators, validate, and verify each new chip.

- Develop tests, testplans, and testing infrastructure for new
graphics architectures. Develop methodologies and tools for validating
test results. Design and implement automated testing strategies. Test
and debug CMODELs, RTL simulation and real silicon.

- Write and run low-level graphics tests which expose
architectural performance characteristics of competitors' graphics
chips. Compare results with nVidia graphics chips. Find shortcomings
and strong points of each. Work with architects to determine
underlying causes. Publish and maintain results. Develop behavioral and
performance models of hardware features defined by chip
architects.Develop and maintain diagnostics and tests for hardware.
Develop and maintain scripted workflows. Develop and maintain
infrastructure such very large multi-platform build environments.
Support development of compilers for interface description languages.
Develop and maintain automated testing infrastructure.

Requirements:

Minimum requirements: Bachelors Degree in relevant discipline(s) (CS,
EE, Math). Advanced degrees helpful.
- Relevant industrial experience preferred. Relevant industries include
PC or workstation graphics hardware or software development, digital
video or image processing, video game software development, rendering
software or tools development. - Strong programming ability: C, C++ and
Perl preferred.



Positions open for System Engineering Team:



Role:

You will be responsible for ASIC and board bring up, validation, and
debug from prototype to production. You will work on cutting edge
technologies such as PCI Express and SATA II and will be required to
perform logic validation and interface characterization of all PC
interfaces to ensure compliance to industry standards. You will debug
complex ASIC and board issues related to logic design, signal integrity
and power delivery in a high energy work environment, with a team that
is the best in the business. You will also work on stress testing,
thermal characterization and stability improvement. You will also work
closely with Application Engineering teams to resolve customer issues
in time critical environment.


Minimum Requirements:

You should be an engineer with 3-7 years of experience in board
design/bring up/validation. You should be familiar with PCB layout and
high speed board design issues, PC architecture, AMD & Intel CPU
interfaces, and bus protocols such as IDE, PCI, PCI-Express, SATA, USB,
etc. You should have In-depth knowledge of signal integrity, EMI/EMC
and Analog interface characterization. You must be well versed in the
usage of high end test and measurement tools such as DSOs, Logic
analyzers and bus exerciser/analyzers.

What we expect from you:
If you find this opening interesting then kindly forward your profile
in word format along with your current CTC & expected CTC details to
[email protected] ASAP. Kindly inform the same to your
colleagues and friends.

Positions at Bangalore, India

Thanks & Regards,

Komal Tripathi.

____________________________

PriorityONE Consulting

Your Success is our PRIORITY # 1!

Contact me:

India Mobile: +91-9945341452.

Direct Lines: 080-41313872

E-mail: [email protected]



PriorityONE Consulting provides the best technical talent to suit the
needs of

high end software companies for the entire technology and hierarchy
spectrum.

We serve our clients and our candidates with respect and commitment.


Visit us at:

www.priorityoneindia.com


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Frank @ CN wrote:
> Hi, there:
>
> In my application, a RAM needs to be written/read from two sets of
> data/address ports
> simultaneously. However, in the ASIC library I can only instantiate some
> single port RAM
> and RAM which can be written in one port and read from the other port.
>
> How shall I solve this problem?
>
> Thank you.


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