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Old 03-02-2006, 08:13 AM
Frank
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Default Re: How do I make dual-port RAM from single port RAM?


"Derek Simmons" <[email protected]> wrote in message
news:[email protected] ups.com...
> I've been trying to follow your problem and now have time to lend some
> help. I'm going to approach this from a black-box design point of view.
>
>
> First question is how are in implementing it or what language are you
> using (VHDL, Verilog or something else)?
>
> What size device are you looking to create (data and address bus
> width)? Or are you trying to create a library device?
>
> What device and signals in the original design being used?
>
> Derek
>


Thank you Derek.
I received an FPGA design in RTL Verilog and need to convert into ASIC. Now
everything is done except this memory issue. The design of the RTL is
unfamiliar to
me so large modifications are meant only for the long run. Requesting
redesign of
the memory isn't an option either.

The culprit RAMs are 8 instances of 130*6bit DPRAM. My entire design is 200K
gate without RAM. My short term goal is to use the existing RAMs in the ASIC
library and perform successful synthesis & gate level simulation, with ASIC
RAMs
included in the system (I could simulate with Xilinx RAM and ASIC for the
rest).

What ideas do you have for my description?



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