This is not guaranteed to work by the language definition. The
execution order of the statements in the sequential block is
guaranteed, and each blocking assignment is guaranteed to update the
reg before the next statement executes (which is why it is called a
blocking assignment). But as you feared, the continuous assignments to
the wires on the outside of the ports could occur in any order, as
could the actual updates to the wires resulting from those continuous
assignments. It is definitely not the case that continuous assignments
triggered by a blocking assignment will always be evaluated before the
statement following the blocking assignment; there are simulators that
will not do this.

A real simulator will not use a nondeterministic ordering, and the
ordering it uses may allow this code to work. For example, it might
always append events to the event queue, in which case the output nets
would update in the same order as the regs. But the language
definition says that this is not guaranteed.

You might be able to get something guaranteed by using nonblocking
assignments for your Update reg. A nonblocking assignment is
guaranteed not to update until after all your blocking assignments and
associated continuous assignments are complete.