I have a SystemVerilog question. The LRM says a module port can be an
array, but I can't figure out the syntax to connect to it in the
instantation.

Example:

module foo;
wire [7:0] dat0;
wire [7:0] dat1;

bar bar0(.baz ({dat1, dat0}));
endmodule // foo

module bar(input wire [7:0] baz [2]);

endmodule // bar

When I run that through Questa, I get an error:
# ** Error: (vsim-3843) array_in.sv(5): Illegal packed type to unpacked
type connection for port 'baz'.

I've tried several variations on that but haven't gotten it right. How
are you supposed to connect different signals to elements of an input
array? Do I have to put them in an array first?

TIA.

-cb