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Old 05-04-2005, 01:43 PM
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Default Re: Stating Timing Analysis - Timing-Critical Paths & False Paths

"Chloe" <[email protected]> wrote in message
news:[email protected]
> Hello everyone,

> My question is: what do you define as TIMING-CRITICAL paths? Any useful
> examples given would be appreciated.
> The idea of defining false paths is to avoid the synthesis tool from
> deriving unnecessary logic, I/O replication, and/or false timing
> constraint failure report. Are these false paths derived using the STA
> tool first, isolated in the false paths list, and then the tool rerun
> for further STA? How does the designer determine what the false paths
> are before STA?

Hi Chloe,

Timing critical path are those path that do not meet your timing. What
normally happens is that after synthesis the tool will give you a number of
path which have a negative slag. The first thing you would do is to make
sure those path are not false or multicycle since it that case you can just
ignore them. This can be quite a lengthy and difficult task but there are
now tools coming to market which can detect these path automatically,
Fishtail automation and BluePearl are 2 companies that springs to mind.


> Please forgive the triviality of the questions as I am very new at
> this.
> Thanks very much in advance.
> Kind regards,
> Chloe

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