Hello everyone,

This was written by Mark Johnson on Oct 17 1992, and for some reason, I
could not reply to the post (perhaps it's too old). Anyway, here is
what he wrote regarding false paths in static timing analysis:

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IN THE DOMAIN OF STATIC TIMING ANALYSIS (if you don't know
what static timing analysis is, ignore the remainder of
this paragraph), "false path" means a path through the
logic/circuit that does exist, but which is known by
the human designer to NOT be a timing-critical path.
For example, asynchronous clear/reset paths. The static
timing analyzer reports them to the human, and the human
judges them to be "false", i.e. these paths are not
speed critical. Usually the human then puts them into
a list of "dont-annoy-me-any-more" paths, the
"known-false-paths" list, and thereafter the timing
analyzer refrains from reporting them.

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My question is: what do you define as TIMING-CRITICAL paths? Any useful
examples given would be appreciated.

The idea of defining false paths is to avoid the synthesis tool from
deriving unnecessary logic, I/O replication, and/or false timing
constraint failure report. Are these false paths derived using the STA
tool first, isolated in the false paths list, and then the tool rerun
for further STA? How does the designer determine what the false paths
are before STA?

Please forgive the triviality of the questions as I am very new at
this.

Thanks very much in advance.

Kind regards,
Chloe