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Old 12-14-2004, 06:59 AM
Paul Uiterlinden
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Default Re: Making output-port to bi-directional-port!

Vick wrote:
> Hello everyone,
>
> I am facing problems making an output-port to a bi-directional port.
> [snip]
>
> inout [31:0] AD; // Note: This gives error when AD declared as
> inout-port //
> reg [31:0] AD; // Declaring: wire [31:0] AD also didnt compile!


One does not preclude the other. AD can be inout and reg at the same time:

inout [31:0] AD;
reg [31:0] AD;

Since Verilog 2001 the two lines can be combined into one line (if I'm
not mistaken):

inout reg [31:0] AD;

> [snip]
>
> else assign AD = 8'hzzzzzzzz;


This should be 32'hzzzzzzzz;. It don't know what happens in your case,
specifying the width as 8, supplying 32 bits. I don't know Verilog that
well.

Paul.
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