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Old 12-13-2004, 05:29 PM
Vick
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Default Making output-port to bi-directional-port!

Hello everyone,

I am facing problems making an output-port to a bi-directional port.

//////////////////////////////////////////////////////
///// (A) Here is the code, which compiles correctly:
/////////////////////////////////////////////////////
module SRAMinterface (AD,clock, WE, RE)

input clock;
input WE;
input RE;


output [31:0] AD;
reg [31:0] AD;

reg [7:0] A;
reg [7:0] B;
reg [7:0] C;
reg [7:0] D;

reg E,F;

always @(posedge clock)
begin
if (E==F)
begin
assign AD = {A,B,C,D};
end

else assign AD = 8'hzzzzzzzz;
end
end
endmodule


/////////////////////////////////////////////////////////////////
//// (B) Here is the Code, which gives the error as shown below:
////////////////////////////////////////////////////////////////

module SRAMinterface (AD,clock, WE, RE)

input clock;
input WE;
input RE;


inout [31:0] AD; // Note: This gives error when AD declared as
inout-port //
reg [31:0] AD; // Declaring: wire [31:0] AD also didnt compile!

reg [7:0] A;
reg [7:0] B;
reg [7:0] C;
reg [7:0] D;

reg E,F;

always @(posedge clock)
begin
if (E==F)
begin
assign AD = {A,B,C,D};
//// The error is shown at this line saying Incompatible inout port
////
end

else assign AD = 8'hzzzzzzzz;
end
end
endmodule



I tried the following but none of them compiled:

(1) I know that Inout-ports both internally & externally must always
be net type. So I declared: <wire [31:0] AD > in (B) above

(2) The LRM clearly says that any continuous assignment within any
procedural-statements, namely always (or) initial, has to be a
register, So retained AD as reg while it was declared inout-port.


(3) I also rememeber reading earlier that the Conditional-assignment
needs to be used for bi-directional ports.

So I replaced the above always @(..) block to a conditional assignment
as below:

assign AD = (E==F) ? {A,B,C,D} : 8'hzzzzzzzz;


Is there soemthing very obvious, I am missing!!
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