Hi experts,

I have a question about mismateched "by order" port connection. For
follow example:

-----------------
module child ( A, B, C );
input [0:1] A;
output B, C;

INV i1 ( A[0], B );
INV i2 ( A[1], C );

endmodule

module top;
wire [0:1] top_A;
wire top_B, top_C;

child ins1 ( top_A );

endmodule
------------------

ncelab will give follow error message:
ncelab: 05.10-p001: (c) Copyright 1995-2003 Cadence Design Systems,
Inc.
child ins1 ( top_A );
|
ncelab: *W,CUVWSP (./a.v,14|9): 2 ports were not connected:
B
C

And if I change the instance statement to:
child ins1 ( top_A, top_B, top_C, a );

Then ncelab will output:
ncelab: 05.10-p001: (c) Copyright 1995-2003 Cadence Design Systems,
Inc.
child ins1 ( top_A, top_B, top_C, a );
|
ncelab: *E,CUVWLP (./a.v,14|9): Too many module port connections.

My question is: I cannot find corresponding information about
mismatched "by order" port connection in the LRM (IEEE 1364-2001). Do
above ncelab's outputs accord with standard Verilog-2001?

Thanks,
Bin