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Old 07-22-2003, 05:30 PM
Spam Hater
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Default Re: Verilog based PCB design flow?


Step 1) Create netlist from Verilog source.
Step 2) Read netlist into PCB editor.

I think you're missing step 1. Verilog is not a netlist; netlists are
created from Verilog.


On 21 Jul 2003 01:19:54 +0200, Petter Gustad
<[email protected]> wrote:

>Spam Hater <[email protected]> writes:
>
>> Verilog netlist? Do you mean a netlist created from a Verilog
>> structural representation? If so, OrCAD can do that.

>
>I mean a Verilog netlist I write in a text editor which instantiate
>components used on the PCB. I would be happy if somebody could point
>me to some documentation (URL's) on how to do this in OrCAD.
>
>
>Petter


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