[email protected] (walter) wrote in message news:<

[email protected] com>...

> Hi All,

>

> I am not sure if this is the right place to post the title. But I will

> be very appreciated if any one can help.

>

> When synthesis with Synopsys Design Compiler, I got the message :

>

> Warning: Design 'ooo' contains 1 high-fanout nets. A fanout number of

> 1000 will be used for delay calculations involving these nets.

> (TIM-134)

>

> 1. Is the warning quite important?
DC uses the following formula to calculate net capacitance:

NET CAP = SUM OF ALL Cpins + Wire Cap, where:

Cpin is input capacitance of each driven pin;

Wire Cap is net capacitance, which is calculated from WLM using net

fanout and design area info. During Design optimization, DC need to

recalc NET CAP value capacitance every time it adds / removes net

loads.

However, for high fanout nets different formula is used:

NET CAP = high_fanout_net_threshold * high_fanout_net_pin_capacitance

+ Wire Cap

where high_fanout_net_threshold and high_fanout_net_pin_capacitance

are two initially predefined DC variables.

So, if net fanout exceeds high_fanout_net_threshold , NET CAP becomes

fixed and will not be recalculated every time DC makes incremental

changes.

> 2. How can I identify the high-fanout nets?
You may run "report_net_fanout -high_fanout" command (see help for

command options)

> 3. How can I fix the warning?
Use set_ideal_net or set_ideal_network commands to exclude net from

any optimizations.

> I guess it might be reset or clock signal.

> So I use

> set_drive 0

> set_dont_touch_network

> on all clocks and reset

> But still got the warning.
Regards,

Alexander Gnusin

www.TCLforEDA.net