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Old 07-02-2003, 10:07 AM
Uwe Bonnes
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Default Re: A synthesis question about "high-fanout nets"

walter <[email protected]> wrote:
: Hi All,

: I am not sure if this is the right place to post the title. But I will
: be very appreciated if any one can help.

: When synthesis with Synopsys Design Compiler, I got the message :

: Warning: Design 'ooo' contains 1 high-fanout nets. A fanout number of
: 1000 will be used for delay calculations involving these nets.
: (TIM-134)

: 1. Is the warning quite important?

For a high speed design mostly.

: 2. How can I identify the high-fanout nets?

Look at your design, look at the syntesis report and logs.

: 3. How can I fix the warning?
: I guess it might be reset or clock signal.
: So I use
: set_drive 0
: set_dont_touch_network
: on all clocks and reset

Try to use the FPGA family specific resources for that net. E.g. on Xilinx
for the reset line, you can use the STARTUP block and connect your generated
reset signal to that block.

Bye
--
Uwe Bonnes [email protected]

Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt
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