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Old 07-02-2003, 05:52 AM
walter
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Default A synthesis question about "high-fanout nets"

Hi All,

I am not sure if this is the right place to post the title. But I will
be very appreciated if any one can help.

When synthesis with Synopsys Design Compiler, I got the message :

Warning: Design 'ooo' contains 1 high-fanout nets. A fanout number of
1000 will be used for delay calculations involving these nets.
(TIM-134)

1. Is the warning quite important?
2. How can I identify the high-fanout nets?
3. How can I fix the warning?
I guess it might be reset or clock signal.
So I use
set_drive 0
set_dont_touch_network
on all clocks and reset
But still got the warning.
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