FPGA Whitepapers/ CPLD Whitepapers

WP151 - System ACE Configuration Solutions for Xilinx FPGAs

Submitted by fpgawhitepaper on September 13, 2008 - 10:29pm
Whitepaper By: 
Xilinx

Design techniques for electronic systems are constantly changing. In industries at the heart of the digital revolution, this change is especially acute.

WP161 - Comparing Virtex-II and Stratix Logic Utilization

Submitted by fpgawhitepaper on September 13, 2008 - 10:28pm
Whitepaper By: 
Xilinx

New programmable logic circuits provide an evergrowing set of architectural elements.

WP217 - Estimating Actual Output Timing Without Board Simulation

Submitted by fpgawhitepaper on September 13, 2008 - 10:28pm
Whitepaper By: 
Xilinx

This document can help designers obtain more accurate I/O timing data without the need for boardlevel IBIS or SPICE simulations.

WP130 - Broadband Access

Submitted by fpgawhitepaper on September 13, 2008 - 10:28pm
Whitepaper By: 
Xilinx

The Internet continues to expand at an enormous rate, and the worldwide modem market will continue to be buoyed by this growth as the default solution for residential Internet access.

WP131 - Media (Residential) Gateways

Submitted by fpgawhitepaper on September 13, 2008 - 10:28pm
Whitepaper By: 
Xilinx

The primary function of the media gateway is to provide broadband connectivity to the home through cable, xDSL, satellite, and wireless.

WP138 - Voice-Data Convergence—Voice Over IP

Submitted by fpgawhitepaper on September 13, 2008 - 10:27pm
Whitepaper By: 
Xilinx

This paper gives an overview of voice-data convergence technologies and how Xilinx high volume programmable devices can be used to overcome some of the significant challenges facing the designers of

WP233 - IEEE 802.17, Resilient Packet Ring Networks Enabled by FPGAs

Submitted by fpgawhitepaper on September 13, 2008 - 10:27pm
Whitepaper By: 
Xilinx

Resilient Packet Ring (RPR) is a transport technology that has been available for several years. The standard IEEE 802.17 specifies the transport.

WP237 - What are OFFSET Constraints?

Submitted by fpgawhitepaper on September 13, 2008 - 10:26pm
Whitepaper By: 
Xilinx

A fundaental timing constraint is the OFFSET constraint.

WP246 - Power Consumption in 65 nm FPGAs

Submitted by fpgawhitepaper on September 13, 2008 - 10:11pm
Whitepaper By: 
Xilinx

With the introduction of the Virtexâ„¢-5 family, Xilinx is once again leading the charge to deliver new technologies and capabilities to FPGA consumers.

WP262 - Designing Multiprocessor Systems in Platform Studio

Submitted by fpgawhitepaper on September 13, 2008 - 10:11pm
Whitepaper By: 
Xilinx

Embedded processing requirements are growing at a rapid pace and system architects are turning towards multiprocessor designs to solve the problems of burgeoning complexity and inadequateness found i

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