FPGA Whitepapers/ CPLD Whitepapers

WP333 - FIFOs in Virtex-5 FPGAs

Whitepaper By: 
Xilinx

In a First-In First-Out (FIFO) memory subsystem, data is written and retrieved in exactly the same order; the first data written into the memory is the first data read out of the memory.

WP323 - Signal Integrity: Tips and Tricks

Whitepaper By: 
Xilinx

Signal integrity (SI) engineering has become a necessary requirement for today’s high-speed logic signals.

WP321 - IBIS Model Usage

Whitepaper By: 
Xilinx

Models of I/O characteristics are used to accurately simulate the signal behavior on a printed circuit board.

WP322 - Bit Error Ratio: What Is It? What Does It Mean?

Whitepaper By: 
Xilinx

Bit Error Ratio (BER) is used to measure the performance of a communications link.

WP320 - It's Not the Same Old PCB Anymore

Whitepaper By: 
Xilinx

Signal integrity (SI) engineering is difficult to avoid in current electronic systems. It is needed now more than ever to save time and money, and to enable the design to work reliably.

WP221 - Static Power and the Importance of Realistic Junction Temperature Analysis

Whitepaper By: 
Xilinx

Total power consumption of a board or system is important; each FPGA or ASIC in a system is beginning to be forced to meet a power budget.

WP152 - Xilinx FPGA Configuration Data Compression and Decompression

Whitepaper By: 
Xilinx

This document provides a brief description of the Xilinx bitstream compression algorithm based on the LZ77 scheme.

WP115 - Data Encryption using DES/Triple-DES Functionality in Spartan-II

Whitepaper By: 
Xilinx

Today’s connected society requires secure data encryption devices to preserve data privacy and authentication in critical applications.

WP124 - Xilinx at Work in Digital Modems

Whitepaper By: 
Xilinx

This white paper gives an overview of digital modem technologies and how Xilinx high volume programmable devices can be used to implement complex system level glue in digital modem designs.

WP228 - Using Non-standard Voltages with CoolRunner-II CPLDs

Whitepaper By: 
Xilinx

Xilinx CoolRunnerTM-II CPLDs support the 5%) and 3.0V (+/- 5%) I/O levels with the Xilinx CoolRunner-II CPLDs.

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