FPGA Whitepapers/ CPLD Whitepapers

FPGAs - Under the Hood

Submitted by fpgawhitepaper on September 11, 2008 - 5:57am

High-level design tools offer field-programmable gate array (FPGA) technology to engineers and scientists who have little or no digital hardware design expertise.

40-nm FPGAs and the Defense Electronic Design Organization

Submitted by fc on July 1, 2008 - 3:41pm
Whitepaper By: 
Altera

With Altera’s introduction of 40-nm FPGAs, the design domains of military electronics that can be addressed with

DPA Circuitry and rx_dpa_locked Signal Behavior in Stratix III Devices

Submitted by fc on June 29, 2008 - 8:00pm
Whitepaper By: 
Altera

The receiver PLL provides eight clock phases to the DPA circuitry. The eight clock phases are separated by 45° and at a frequency equal to the serial data rate.

Altera at 40 nm: Jitter-, Signal Integrity-, Power-, and Process-Optimized Transceivers

Submitted by fc on May 29, 2008 - 8:00pm
Whitepaper By: 
Altera

Technology advancement for the semiconductor industry is largely driven by Moore’s Law in that the number of

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