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Verification Management

Mentor Forum for Verification - Crossing the barrier to Advanced Functional Verification - Stevenage, UK

When: 
Jun 21 2012 - 9:30am

Overview

Traditionally FPGA design flows do not include large amounts of verification prior to heading into the lab. Today’s FPGA devices however, are growing dramatically in both size and complexity such that FPGA design teams verification needs almost match those previously reserved for ASIC design.

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Mentor Forum for Verification - Crossing the barrier to Advanced Functional Verification - Munich, Germany

When: 
Jun 12 2012 - 9:30am

Overview

Traditionally FPGA design flows do not include large amounts of verification prior to heading into the lab. Today’s FPGA devices however, are growing dramatically in both size and complexity such that FPGA design teams verification needs almost match those previously reserved for ASIC design.

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Mentor Forum for Verification - Crossing the barrier to Advanced Functional Verification - Sophia Antipolis, France

When: 
Jun 5 2012 - 9:30am

Overview

Traditionally FPGA design flows do not include large amounts of verification prior to heading into the lab. Today’s FPGA devices however, are growing dramatically in both size and complexity such that FPGA design teams verification needs almost match those previously reserved for ASIC design.

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