Cliff Cummings Verilog-2001 Design & Best Coding Practices Class - Santa Clara

This webinar will focus on the highest value tools and techniques for improving test stimulus, debug effectiveness and simulation throughput. One of the most common verification process improvement opportunities is being able to more easily create test cases, including leveraging standard bus interfaces like PCIe for stimulating your system.

This is one of the most comprehensive IC Layout training programs in the industry. It covers semiconductor process technologies from 0.35um BCD down to 14nm CMOS and explores Analog, Mixed-Signal and RF layout skills. Instructors are seasoned engineers with deep understanding of physical design, class assignments and practice examples are realistic and are taken from actual design projects.

Cadence Design Systems, Bldg. 10 Auditorium
2655 Seely Ave.
San Jose, CA 95134

Join us on October 10th for our Mixed-Signal Technology Summit. Experts from Cadence and other leading companies will present the latest mixed-signal design methodologies. Find out how they applied new techniques to meet their aggressive project goals.

This webinar articulates a methodology for verification planning based on actual experience at Freescale Semiconductor. The verification planning process described in this session is streamlined for derivatives and comprehensive enough for new design and verification development. It explains a complete verification flow including verification strategy, planning, change management, and closure.