Cliff Cummings: System Verilog OVM/UVM Training (3 days) - Santa Clara, Ca

Cliff Cummings: System Verilog OVM/UVM Training (3 days) - Santa Clara, Ca
Mar 31 2014 - 9:00am

UVM is the unified future of SystemVerilog Verification

The good news is that the Universal Verification Methodology (UVM) is largely the same thing as the Open Verification Methodology (OVM) with a different first letter and a few enhancements including capabilities donated from VMM. This course teaches OVM & UVM noting the minor changes that differentiate the two methodologies.

Intelligent Testbench Automation: Accelerating Coverage Closure Workshop - Fremont, CA

Oct 25 2012 - 9:30am

The Mentor Graphics testbench automation product is the first coverage-driven stimulus generation solution to use intelligent algorithms to synthesize meaningful testbench sequences while allowing the user to set verification goals and priorities prior to simulation.

Productivity & Coverage for UVM

Sep 19 2012 - 8:30am

As SoC and ASIC designs continue growing in both size and complexity and FPGA devices now becoming SoCs themselves, design and verification teams are constantly searching for ways to increase their verification productivity and design quality to keep up with this growing challenge. There have been several methodologies introduced in the past that are aimed at addressing these challenges.

Easier UVM: Functional Verification for Mainstream Designers

The Easier UVM webinar provides an introduction to the guidelines for learning and using UVM, the Universal Verification Methodology for SystemVerilog. It is aimed at mainstream designers rather than power users specialising in verification. The webinar comprises two sessions, on successive days, each session being one hour long.


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