Easier UVM: Functional Verification for Mainstream Designers

The Easier UVM webinar provides an introduction to the guidelines for learning and using UVM, the Universal Verification Methodology for SystemVerilog. It is aimed at mainstream designers rather than power users specialising in verification. The webinar comprises two sessions, on successive days, each session being one hour long.


Web page:

Facebook  Twitter  Linkedin  YouTube      RSS


Check out FPGA related videos

Find Us On Facebook