Cadence

Cadence Palladium XP Platform Chosen by Mellanox Technologies to Shorten Development Time of Interconnect Products

Cadence Palladium XP Platform Enables Mellanox to Accelerate System Integration by Effectively Accelerating Hardware and Software Integration

Front-End Design Summit: Physically Aware Design - San Jose, CA

Front-End Design Summit: Physically Aware Design - San Jose, CA
When: 
Dec 5 2013 - 9:00am

Save closure time and boost performance by incorporating knowledge of physically aware design early into your front-end design implementation flow

Signoff Summit: The Fastest Path to Design Signoff - San Jose, CA

Signoff Summit
When: 
Nov 21 2013 - 8:30am

Join us on November 21 at our San Jose headquarters for the latest in a series of Signoff Summits that focus on the multiple aspects of chip design signoff. Industry experts, including Anirudh Devgan (Cadence), Richard Trihy (Globalfoundries), and Jim Hogan (EDA Visionary), will comment on the direction of design signoff.

Mixed-Signal Technology Summit (San Jose, CA)

Mixed-Signal Technology Summit (San Jose, CA)
When: 
Oct 10 2013 - 8:00am

Cadence Design Systems, Bldg. 10 Auditorium
2655 Seely Ave.
San Jose, CA 95134

Join us on October 10th for our Mixed-Signal Technology Summit. Experts from Cadence and other leading companies will present the latest mixed-signal design methodologies. Find out how they applied new techniques to meet their aggressive project goals.

CDNLive India 2013 - Bangalore, India

CDNLive India 2013 - Bangalore, India
When: 
Oct 9 2013 - 9:00am

CDNLive India 2013

October 9-10, 2013
Park Plaza Hotel
Bangalore

THANKS TO AN OVERWHELMING RESPONSE REGISTRATION FOR CDNLIVE INDIA IS NOW CLOSED.

If you are interested in attending CDNLive India, please contact your Cadence representative.

CDNLive India 2013 - Bangalore, India

CDNLive India 2013 - Bangalore, India
When: 
Oct 9 2013 - 9:00am

CDNLive India 2013

October 9-10, 2013
Park Plaza Hotel
Bangalore

THANKS TO AN OVERWHELMING RESPONSE REGISTRATION FOR CDNLIVE INDIA IS NOW CLOSED.

If you are interested in attending CDNLive India, please contact your Cadence representative.

ARM Acquires Advanced Display Technology from Cadence

Cadence and ARM Deepen Collaboration on High-End Mobile Device Development

Best Practices in Verification Planning - webinar

Best Practices in Verification Planning - webinar
When: 
Sep 4 2013 - 9:00am

This webinar articulates a methodology for verification planning based on actual experience at Freescale Semiconductor. The verification planning process described in this session is streamlined for derivatives and comprehensive enough for new design and verification development. It explains a complete verification flow including verification strategy, planning, change management, and closure.

Renesas Licenses Cadence's Tensilica ConnX D2 DSP for Next-Generation IoT Chip, HiFi Audio DSP

SAN JOSE, CA--(Marketwired - August 28, 2013) - Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that as part of their Smart Society initiative, Renesas Electronics Corporation has licensed the Tensilica ConnX D2 DSP (digital signal processor) for a next-generation chip designed for Internet of Things (IoT) applications.

Realtek Licenses Cadence's Tensilica HiFi Audio/Voice DSP IP Core

Realtek's Chips Designed for PC and Mobile Wireless Applications

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