Home
World's Largest FPGA/CPLD Portal

ASIC

OneSpin Solutions Unveils OneSpin 360 DV Product Family

Bundles Multiple Software Solutions at No Additional Charge, Bucking Industry “Apps” Trend

MUNICH, GERMANY –– February 11, 2013 –– OneSpin Solutions™, provider of innovative formal assertion-based verification (ABV) solutions, announced the bundling of multiple verification tools into its new OneSpin 360™ DV Product Family.

Tags:

ModelSim & Questa: Smarter Simulation - Budapest, HU

When: 
Oct 30 2012 - 8:30am

Today’s FPGAs and ASICs are ever increasing in density and complexity and the result of this is that the design verification is growing at an exponential rate. Engineers have tried to counter this by using faster and faster computers and multi-processing but this is not enough.

Tags:

Productivity & Coverage for UVM

When: 
Sep 19 2012 - 8:30am

As SoC and ASIC designs continue growing in both size and complexity and FPGA devices now becoming SoCs themselves, design and verification teams are constantly searching for ways to increase their verification productivity and design quality to keep up with this growing challenge. There have been several methodologies introduced in the past that are aimed at addressing these challenges.

Tags:

Xilinx Returns to DAC Asking - Why ASIC When You Can Go All Programmable?

Xilinx exhibits for first time since 2002 to mark FPGA transition to All Programmable devices and the introduction of the Vivado Design Suite as a bridge from ASICs

Tags:

Mentor Forum for Verification - Crossing the barrier to Advanced Functional Verification - Stevenage, UK

When: 
Jun 21 2012 - 9:30am

Overview

Traditionally FPGA design flows do not include large amounts of verification prior to heading into the lab. Today’s FPGA devices however, are growing dramatically in both size and complexity such that FPGA design teams verification needs almost match those previously reserved for ASIC design.

Tags:

Mentor Forum for Verification - Crossing the barrier to Advanced Functional Verification - Munich, Germany

When: 
Jun 12 2012 - 9:30am

Overview

Traditionally FPGA design flows do not include large amounts of verification prior to heading into the lab. Today’s FPGA devices however, are growing dramatically in both size and complexity such that FPGA design teams verification needs almost match those previously reserved for ASIC design.

Tags:

Mentor Forum for Verification - Crossing the barrier to Advanced Functional Verification - Sophia Antipolis, France

When: 
Jun 5 2012 - 9:30am

Overview

Traditionally FPGA design flows do not include large amounts of verification prior to heading into the lab. Today’s FPGA devices however, are growing dramatically in both size and complexity such that FPGA design teams verification needs almost match those previously reserved for ASIC design.

Tags:

Facebook  Twitter  Linkedin  Orkut  YouTube      RSS

 

Check out FPGA related videos

more

Find Us On Facebook