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3D IC Packaging Thermo-Mechanical Short course at IMAPS - webinar

3D IC Packaging Thermo-Mechanical Short course at IMAPS
When: 
Mar 11 2013 - 9:00am

3D IC Packaging Thermo-Mechanical Short course at IMAPS

The course will be held on March 11th. This is a unique course with plenty of high level information suited for anyone with interest in packaging of 3D ICs.

Altera and TSMC develop heterogeneous 3D IC test vehicle

Eeek alors! The net is buzzing with the news that the folks from Altera and TSMC have just announced their joint development of what they describe as “The world’s first heterogeneous 3D IC test vehicle using TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) integration process” (see also Dylan McGrath’s column TSMC, Altera team on 3-D IC test vehicle).

New Dimension in Chips

What 3D ICs Mean for the FPGA Industry

by Kevin Morris

3D is one of the hottest buzzwords these days. Every marketeer worth his salt is trying to find a way for the next “new thing” to be plausibly labeled as “3D.” 3D is cool. We see it in movies. The bad guys jump right out from the screen. 3D is real, vibrant, and immersive. 2D is, well, flat and boring.

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