20nm

Xilinx Kintex UltraScale FPGAs are First 20nm Devices to Achieve PCI Express Compliance

Submitted by fc on May 1, 2014 - 12:00am

Integrated blocks for PCI Express enable high-performance applications

Xilinx tapes out first Virtex UltraScale device

Submitted by fc on January 21, 2014 - 1:00am

Xilinx has taped out its first Virtex UltraScale device, which it describes as the 'industry's only high end 20nm offering'.
Manufactured using TSMC's 20SoC process, the VU095 features an asic like programmable architecture which, according to Xilinx, enables up to 2x more realisable system level performance and integration.

Xilinx’ 20nm All Programmable UltraScale portfolio shipping now: plans for 4.4M logic cell device

Submitted by fc on December 10, 2013 - 1:00am

Xilinx has announced the availability of its 20nm All Programmable UltraScale portfolio with product documentation and Vivado Design Suite support. The new product portfolio extends Xilinx’s Kintex and Virtex FPGA and 3D IC families, with the superior gate density of TSMC’s 20SoC process.

Xilinx 20nm All Programmable UltraScale Portfolio Now Available with ASIC-class Architecture and ASIC-strength Design Solution

Submitted by fc on December 10, 2013 - 1:00am

Detailed device tables, product documentation, design tools, and methodology support now available for Kintex mid-range and Virtex high-end 20nm UltraScale families

Altera launches 20nm tools

Submitted by fc on December 2, 2013 - 1:00am

Altera has come up with development tools for 20nm IC design, based on TSMC’s 20 nm process technology. The annual software subscription is $2,995 for a node-locked PC license.

Xilinx ships first 20nm fpgas

Submitted by fc on November 13, 2013 - 1:00am

Xilinx has begun shipping its first 20nm fpga chips to customers.
Manufactured by TSMC, the UltraScale devices feature an asic like programmable architecture which, according to Xilinx, enables up to 2X more realisable system level performance and integration.

Mentor Forum - Beijing, China

Submitted by fc on September 2, 2013 - 10:25am
Mentor Forum - Beijing, China
When: 
Sep 3 2013 - 9:00am

Wally Rhines, CEO and Chairman of Mentor Graphics, keynotes this free event, one in a series of Mentor Forums in Asia this year. The VIP speaker is Dr. Shawn Han, VP of Foundry Marketing, Samsung. Mentor Forums are free and open to anyone.

Topics include:

New challenges of 20nm, and 16/14nm FinFET
3D-IC design
Custom and AMS methodology
DFM-driven place&route

Imec reveals method of damage free cryogenic etching of ultralow-k dielectrics

Submitted by fc on July 9, 2013 - 12:00am

New method allows IC manufacturers to reach scaling levels at 20nm and beyond, without compromising speed and device cross-talk

SEMICON WEST, San Francisco (USA) – July 09, 2013 – Imec today announced a cryogenic etching method that protects the surface of porous ultralow-k dielectrics against excessive plasma induced damages.

GLOBALFOUNDRIES demonstrates 3D TSV capabilities on 20nm technology

Submitted by fc on June 4, 2013 - 12:00am

GLOBALFOUNDRIES announced the accomplishment of a key milestone in its strategy to enable 3D stacking of chips for next-generation mobile and consumer applications. At its Fab 8 campus in Saratoga County, N.Y., the company has demonstrated its first functional 20nm silicon wafers with integrated Through-Silicon Vias (TSVs).

Mentor Graphics and GLOBALFOUNDRIES Deliver 20nm Design Kits for Advanced Design Enablement

Submitted by fc on May 31, 2013 - 12:00am

WILSONVILLE, Ore., May 30, 2013—Mentor Graphics Corp. (NASDAQ: MENT) today announced it has collaborated with GLOBALFOUNDRIES to deliver 20nm design kits for the Olympus-SoC™ netlist-to-GDS platform. The design kit enables mutual customers to achieve the best performance, power and area with faster design closure times.

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