vlsi/embedded cv with 3.6 years experience

AMOLKUMAR SAKHARE Email: - [email protected]
MS (TELECOMMUNICATION & NETWORKING) [email protected]

Phone No: + 91- 9739095570

Career Objective
To pursue a challenging career that gives a scope to enhance my knowledge, skills and research abilities in a professionally managed organization.

Experience Summary
• Experience in Wireless and Avionics domain
• Total 3.6 plus years of experience in VLSI / Embedded Systems
• 2.6 years of experience in VLSI Design & Verification
• 1 plus years of experience in Embedded Systems
• Experience in writing System Verilog Testbench
• Experience in the field of development of IP and verification of designs
• Good experience on Digital design, RTL coding using VHDL, Verilog HDL
• Knowledge of Xilinx FPGA : Virtex, Spartan
• Modeling Test Benches as well as implementation of directed and random test cases
• Knowledge in all aspects of Design Life Cycle through Specification, Design Engineering, Modeling, Integration, Debuging & Verification
• Knowledge of 8 bit / 16 bit Microcontroller
• Proficient in creating Test Plan, Test Cases and Test Result from Functional description models, Functional Specifications and State Flow Diagram.
• Extensive experience in Unit Testing using IBM RTRT (Rational Test Real Time)
• Knowledge in PCB Designing

Professional Experience
• Currently working as Software Engineer in Softwares House Private Ltd., Banglore from Feb 2008 to till date
• Worked as Assistant Engineer-VLSI in Silicon Interfaces Private Ltd., Mumbai from October 2006 to Jan 2008
• Worked as VLSI Design Engineer in Ni Logic Private Ltd., Pune from Jan 2003 to April 2004

Technical Skills
Programming Languages : C, C++, Perl, VB6
Modeling Languages : VHDL, Verilog HDL, System Verilog
Operating Systems : LINUX, WINDOWS
Synthesis Tools : Xilinx ISE, Leonardo spectrum
Simulation Tools : Modelsim, NC-Sim

Embedded Tools : Keil µV3, MikroC, IBM RTRT
Debuggers : gdb
RTOS : VxWorks

Database : Oracle
Application : MS-Office, MS-Visio, Rational Studio
Protocols : IEEE 802.11a/b/g, AMBA-AHB, RISC CPU, ARINC 429,
UART, I2C and SPI

Projects: (starting from the most recently executed)
Project #1 : FADEC (Full Authority Digital Engine Control)
Tested features : Unit Testing and Regression Testing
Tools used : RTRT (Rational Test Real Time), ATGS
Environment : Microsoft Visual C 6

Project Description:
The objective of the project is to allow the engine of a plane to perform at maximum efficiency for a given condition. FADEC is a system consisting of a digital computer called an Electronic Control Unit (ECU) and its related accessories that control all aspects of aircraft engine performance. FADEC works by receiving multiple input variables of the current flight condition including air density, throttle lever position, engine temperatures, engine pressures, and many others. Engine operating parameters such as fuel flow, stator vane position, bleed valve position, and others are computed from this data.

Responsibilities:
• Design Test Plan for each unit to be tested from the functional description diagrams and requirement specifications based on DO178B
• Creating Test script and Test cases as per the Test Plan for each unit based on DO178B
• Execution of Test cases using RTRT
• Analysis code coverage, MCDC, functionality for each unit
• Capture the defects and report it
• Generate Test Results and Test summary report

Project #2 : Navigational Monitor Aid
Tested features : Unit Testing and Regression Testing
Tools used : RTRT (Rational Test Real Time)
Environment : Microsoft Visual C 6

Project Description:
The Navigation aid is sort of marker which aids the traveler in navigation. It is a device external to the vehicle specifically intended to assist navigators in determining their positions or safe course, involves process of planning, reading and controlling. Navigation system generally uses a GPS antenna & a GPS receiver to determine its position and movement of the craft.

Responsibilities:
• Design Test Plan for each unit to be tested from that functional description diagrams and requirement specifications
• Creating Test script and Test cases as per the Test Plan for each unit
• Execution of Test cases using RTRT
• Analysis code coverage, MCDC, functionality for each unit
• Capture the defects and report it
• Generate Test Results and Test summary report

Project #3 : Data Acquisition System
Environment : Embedded C on Keil µV3

Project Description:
Data logging is carried out by a data acquisition system (DAS) which can be used to measure parameters such as temperature and humidity in storage facilities with perishable products. The measurement data are then stored for analysis to improve quality assurance.

Responsibilities:
• Involved in the design and implementation using AT89C51

Project #4 : RFID Based Attendance Monitoring System
Environment : Embedded C on Keil µV3

Project Description:
The main objective of the project is to uniquely identify and to make attendance for a person. The main parts of an RFID system are RFID tag (with unique ID number) and RFID reader (for reading the RFID tag). The EEPROM used for storing the details. The PC can be used for restoring all the details of attendance made.

Responsibilities:
• Involved in the design and implementation using AT89C51

Project #5 : MAC Core for Wireless LAN compatible with IEEE 802.11 a/b/g
Environment : System Verilog on Windows Platform with Questasim 6.3d

Project Description:
IEEE 802.11a/b/g are “high rate” standard wireless LAN operates in 2.4 GHz / 5GHz unlicensed RF Band and can transmit up to 54 Mbps and 11 Mbps. This project describes the function and services required by an IEEE 802.11 compliant device to operate within adhoc and infrastructure network. This project is implemented for both IBSS and Infrastructure network.

Responsibilities:
• Involved in writing the major parts in the verification environment including generators, drivers, interface and scoreboards using SystemVerilog

Project #6 : MAC Core for Wireless LAN compatible with IEEE 802.11 a/b/g
Environment : VHDL on Windows Platform with ModelSim, SPARTAN 3E FPGA

Project Description:
IEEE 802.11a/b/g are “high rate” standard wireless LAN operates in 2.4 GHz / 5GHz unlicensed RF Band and can transmit up to 54 Mbps and 11 Mbps. This project describes the function and services required by an IEEE 802.11 compliant device to operate within adhoc and infrastructure network. This project is implemented for both IBSS and Infrastructure network. The interface on Host side is with AMBA-AHB interface.

Responsibilities:
• Study of IEEE 802.11 a/b/g Protocol
• Involved in the designing and coding of MAC Controller, Header Assembly unit and Media access unit module using VHDL
• Implementation of Automated Test Bench using VHDL for module level and system level
• Debuging of DUT
• Targeting the design to SPARTAN 3E FPGA
• Code Documentation of DUT using MS Visio

Project #7 : AMBA-AHB Bus Interface
Environment : VHDL on LINUX Platform with Cadence NC-Sim

Project Description:
AHB is a new generation of AMBA, is a high performance system bus that supports multiple bus masters. The AHB Interface allows the MAC to be easily connected to AMBA-AHB. The AHB Interface supports 32-bit Data Bus and 32-bit Address bus to the AHB Bus side. The arbitration mechanism is used to ensure that only one master has access to the bus at any one time.

Responsibilities:
• Study of AMBA-AHB Protocol
• Implementation of Automated Test Bench using VHDL for module level and system level
• Debuging of DUT
• Code Documentation of DUT using MS Visio

Project #8 : I2C
Environment : VHDL on LINUX Platform with ModelSim, Virtex 2 FPGA

Project Description:
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between devices. It is most suitable for applications requiring occasional communication over a short distance between many devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data corruption if two or more masters attempt to control the bus simultaneously and designed for 100 Kbps.

Responsibilities:
• Study of I2C Protocol
• Implementation of Directed Test Cases using VHDL for system level
• Debuging of DUT
• Targeting the design to Virtex 2 FPGA
• Code Documentation of DUT using MS Visio

Project #9 : 8-bit RISC CPU
Environment : Verilog HDL on LINUX Platform with ModelSim, Virtex 2 FPGA

Project Description:
This project includes the design and development of a microprocessor titled RISC_CPU where different module were designed, implemented and tested separately and then finally integrated to form one single entity. The CPU is capable of performing Arithmetic operations.

Responsibilities:
• Study of RISC CPU
• Coding of DUT in behavioral style using Verilog HDL
• Implementation of directed test cases using Verilog HDL for system level
• Debuging of DUT
• Implemented on Xilinx Virtex2 FPGA
• Code documentation of DUT

Project #10 : UART
Environment : Verilog HDL on LINUX Platform with ModelSim

Project Description:
It is a Universal Asynchronous Receiver Transmitter. The core performs Serial to parallel conversion on data received from a peripheral device or MODEM and parallel to serial conversion on data received from the host. The core provides a full featured Transmitter-Receiver pair, configurable by software for different speed, character widths and parity.

Responsibilities:
• Study of UART Protocol
• Implementation of directed test cases using Verilog HDL for system level
• Debuging of DUT
• Code documentation of DUT

Project #11 : PC Based Remote Controlled Stepper Motor
Environment : Orcad 9 on Windows Platform

Project Description:
Stepper motors are used for position control in many applications like floppy drives (for magnetic pick up positions), printers (for carriage drive, paper feed and print head positioning etc). In this project we design a PC Based remote control circuit for operating a stepper motor.

Responsibilities:
• Design the circuit manually as well as using CAD

Certifications
• Certificate in PCB (Printed Circuit Board) Designing from ATI-EPI, Hyderabad

Educational Qualification
• MS (Telecommunication & Networking), 2006, 70%, from ITM Business School in academic association with Southern New Hampshire University (USA)
• BE (Electronics engineering), 2002, 62.4% from MIET, Gondia, Nagpur University (Maharashtra)

References
Available on Request

Personal profile
Name : AMOLKUMAR SAKHARE
Passport : Ready
Languages known : English, Hindi, Marathi
Permanent address : Plot no. 11, Om Sai Society,
Duttawadi, Nagpur,
Maharashtra,India – 440023