8 years Experience with Xilinx FPGAs, VHDL, Verilog

Vivek Venugopal
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Contact Information
Dept. of Electrical and Computer Engg.
Virginia Tech, Blacksburg VA 24061
Email: [email protected]
WWW:http://www.vivekvenugopal.net

1205 University Terrace, # D
Blacksburg, VA 24060
Phone: 540-558-8724
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Objective

Obtain a full-time position utilizing abilities in:
*FPGA/ASIC system level design and implementation from algorithm specifications using HDLs and CAD tools

*FPGA hardware/software co-design and modeling of system computation and communication in FPGA enabled clusters
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Research Interests: Cluster FPGAs, Systolic architectures, Reconfigurable Communication synthesis, High Performance Reconfigurable Computing, Hardware acceleration
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Education

Ph.D., Computer Engineering, (Expected 2009); GPA: 3.5
Dissertation: ``Synchronization Synthesis for Large Scale Parallel Streaming Applications''
Advisor: Dr. Cameron .D. Patterson
Virginia Polytechnic Institute and State University, Blacksburg, VA

M.S., Electrical Engineering, December 2003; GPA: 3.78
Thesis:``Hardware Efficient Implementations of Decimation Filters''
Co-Advisors: Dr. Raymond .E. Siferd, Dr. Khalid .H. Abed
Wright State University, Dayton, OH

B.E., Electronics Engineering, June 2000; GPA: 3.75
University of Pune, India
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Research and Experience

Research Assistant Virginia Bioinformatics Institute Blacksburg, VA
May 2009 -- Present
Implement and accelerate simulation codes (epifast and episimdemics) on GPGPU clusters by applying system-level optimization techniques

Research Intern Hughes Network Systems Germantown, MD
Aug 2008 - Dec 2008
System design, partitioning and implementation of communication modules for confidential project on cluster of Xilinx Virtex-4 FPGAs

Research Consultant Advanced Research Computing Corporate Research Center, Virginia Tech
Feb 2007 - Aug 2008
Implemented hardware acceleration for High Performance Computing (HPC) applications using FPGAs and nVIDIA GPUs at the Advanced Research Computing facility.
* Improved performance and speedup of Particle Image Velocimetry (PIV) project on FPGAs and GPUs for the AEther Lab as part of my doctoral research.
* Involved in the system administration and application testing on SGI Altix clusters and Virginia Tech's System X supercomputer consisting of Mac OSX/Linux nodes.

Research Intern Intelligent Automation Inc. (IAI) Rockville, MD
May 2006 - Aug 2006
Designed and implemented communication modules for software GPS receiver and satellite hybrid wiring applications on Xilinx Virtex-4 FPGAs. Demonstrated the successful operation of both projects for renewed funding.
* Designed PRBS generator, correlator for GPS receivers and implemented them on Virtex-4 FPGA development board using a Matlab-Simulink based model.
* Designed and implemented correlator, FFT, IFFT, PRBS generator blocks on ADC08D1500 ADC board, used for prototyping satellite hybrid wiring application.

Research Assistant Configurable Computing Lab (CCM) ECE Dept.,Virginia Tech
Aug 2005 - May 2006
Involved in the design and implementation of a cluster of Xilinx ML310 FPGAs for radio astronomy application.
* Implementation of Aurora protocol over the one-to-one Infiniband connections between the nodes.
* Designed and profiled the software modules(using C) for high speed data transfer to disk drives over RAID partitions from the ML310 FPGAs
* Designed and implemented the UART module (using Verilog) and the real time software (using C) for polling the Xilinx ML310 FPGAs and displaying status messages on the console

Research Assistant Center for Power Electronics Systems ECE Dept.,Virginia Tech
May 2005 - Aug 2005
Developed and implemented various test routines and functionality modules for DSP-FPGA interface board. Various algorithms for the control of machines are implemented using this interface board.

Research Assistant Wright State University ECE Dept.
Jan 2002 - Dec 2003
Designed and implemented low power and hardware efficient decimation filters for sigma-delta ADCs of communication receivers.
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Skills

Simulation: Chipscope, Modelsim SE, Synopsys VCS, Scirocco/VirSim, Cadence NC, HSPICE, IRSIM
Synthesis: Synopsys Design Compiler/PrimeTime, Synplify, Leonardo Spectrum
Implementation: Xilinx ISE, Xilinx EDK
HDLs: VHDL, VERILOG
Programming: C, C++, SystemC, Assembly language, MPI programming, CUDA
System-level modeling: Matlab-Simulink, Ptolemy
Layout: Cadence Diva, Mentor Graphics IC Station
High Speed Digital Board Design: Eagle
Prototyping boards: Xilinx ML310, Xilinx Virtex-II Pro and Virtex-4 development boards, EDT-PCI board
Operating Systems and applications: Windows XP, Unix, Linux, Sun Solaris, Mac OSX, UNIX shell scripting

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Awards

Awarded cash prize towards Doctoral Research by Virginia Tech Graduate Research and Development Fund '08. This prize was utilized towards the purchase of a nVIDIA Tesla GPU card for my doctoral research.

Awarded Runner-up prize for poster presentation in the Engineering category at the 24th GSA Research Symposium 2008 in Virginia Tech. The poster Accelerating Particle Image Velocimetry Algorithms for Biomedical Applications describes the implementation of the FFT based PIV algorithm using hardware accelerators such as nVIDIA GPU and FPGA.

Awarded First prize for poster presentation in the Engineering category at the 23rd GSA Research Symposium 2007 in Virginia Tech. The poster Reconfigurable FPGA-based Clusters: Next Step in Supercomputing addresses the requirement of a reconfigurable framework by using FPGAs for better performance and speedup in High Performance Computing (HPC) systems.
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Relevant publications and presentations

``Accelerating Particle Image Velocimetry Using Hybrid Architectures'', V. Venugopal, C.D. Patterson and K. Shinpaugh, Symposium on Application Accelerators in High Performance Computing, NCSA-UIUC, Champaign, IL, July 2009.

``Accelerating MPIBLAST on System X by using RAMdisks'', V. Venugopal, K. Shinpaugh, G. Zelenka and L. Scharf, 9th LCI International Conference on High-Performance Clustered Computing, NCSA-UIUC, Champaign, IL, April 2008.

``Reconfigurable FPGA-based Clusters: Next Step in Supercomputing'', V. Venugopal and K. Shinpaugh, Advanced Research Computing Technical Report, April 2007.

``ETA:Searching for Low-Frequency Radio Transients'', S.W. Ellingson, J.H. Simonetti, C.D. Patterson, V. Venugopal, S. Cutchins and D.W. Taylor, NSF Annual Progress Report, April 2006.

``ETA Cluster Communications: Physical and Data Link Layers'', V. Venugopal, C.D. Patterson, NSF-ETA Project Technical Report, April 2006.

``The Eight-meter-wavelength Transient Array (ETA)'', J. H. Simonetti, S. W. Ellingson, C. D. Patterson, W. Taylor, V. Venugopal, S. Cutchin, and Z. Boor, American Astronomical Society 207th Meeting, January 2006.

``High Speed Digital Filter Design Using Minimal Signed Digit Representation'', V.Venugopal, K.H. Abed, and S.B.Nerurkar, IEEE Southeast Conference, April 2005.

``Design and Implementation of a Decimation Filter for Hearing Aid Applications'', V. Venugopal, K.H. Abed, and S.B. Nerurkar, IEEE Southeast Conference, April 2005.

``Hardware Efficient Narrow Band FIR Filter", V. Venugopal, R.E. Siferd, K.H. Abed, and S.B. Nerurkar, 45th IEEE MWSCAS Conference, August 2002.

``Low Power Sigma Delta Decimation Filter", S.B. Nerurkar, R.E. Siferd, K.H. Abed, and V. Venugopal, 45th IEEE MWSCAS Conference, August 2002.

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Professional service

Student volunteer: SC'08 conference in Austin, Texas.

Student volunteer: MPI and OpenMP '08 workshop at Virginia Tech.

Student volunteer: SC'07 conference in Reno, Nevada.

Student volunteer: MPI and OpenMP '07 workshop at University of Virginia, Charlottesville.
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Membership in Professional Organizations

Member, ACM
Member, IEEE

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